A “tri-state” signal is a digital logic signal that can assume three possible states: a logic “HIGH” state, a logic “LOW” state, and a “HIGH-IMPEDANCE (HIGH-Z) state”. In the HIGH and LOW states, the tri-state signal may take on respective voltage levels (e.g., about Vdd and about Vss). In the HIGH-Z state, the tri-state signal presents high impedance looking into the circuitry providing the tri-state signal. Moreover, typically, the voltage level of the tri-state signal in the HIGH-Z state is permitted to float.
Tri-state signals can be beneficially employed in conventional binary logic circuits. Assume an integrated circuit (IC) has two available input/output (I/O) pins. If the pins are connected to a conventional binary receiving circuit, each I/O pin is allowed to be either a zero or a one, providing a total of four possible input combinations (00, 01, 10, 11, where “0”=LOW state and “1”=HIGH state). However, if the receiving circuit is capable of detecting the three states of a tri-state signal, a total of nine input combinations (00, 01, 0Z, 10, 11, 1Z, Z0, Z1, ZZ, where “Z”=HIGH-Z state) are possible. Tri-state input signals thus increase the amount of information that can be conveyed into a receiving circuit for a given number of pins.
Overview
The systems, methods, and devices of the inventive subject matter each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the embodiments of the invention as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section titled “Detailed Description,” one will understand how the features of the embodiments of the invention provide benefits that include improving input detection circuitry.
In one embodiment, a circuit to detect signal states is disclosed. The circuit comprises an input node to receive an input signal. The circuit further comprises a state detection circuit to detect a state of the input signal and to generate a detection signal. The state can correspond to at least one of three states. The detection signal can have a level based on the detected state of the input signal. The circuit further comprises a logic discriminator circuit to generate first and second state signals based at least partly on the level of the detection signal. The circuit further comprises a clock detection circuit to generate a clock signal based at least partly on a sequence of logic transitions of the first and second state signals.
In another embodiment, a method to detect input states is disclosed. The method comprises receiving an input signal. The method further comprises generating a detection signal based on detecting a state of the input signal. The state can correspond to at least one of three states. The detection signal can have a level based on the detected state of the input signal. The method further comprises generating first and second state signals based at least partly on the level of the detection signal. The method further comprises generating a clock signal based at least partly on a sequence of logic transitions of the first and second state signals
In another embodiment, an apparatus to detect input states. The apparatus comprises means for receiving an input signal. The apparatus further comprises means for detecting a state of the input signal and to generate a detection signal. The state can correspond to at least one of three states. The detection signal can have a level based on the detected state of the input signal. The apparatus further comprises means for generating first and second state signals based at least partly on the level of the detection signal. The apparatus further comprises means for generating a clock signal based at least partly on a sequence of logic transitions of the first and second state signals.